Increasing the Conversion Speed of the Counter-Ramp Analog-to-Digital Converter Based on Starting with Suitable Count

Abstract

Abstract: In this paper, a proposed technique is designed and implemented for increasing the conversion speed of the Counter-Ramp A/D converter. It depends on starting with suitable count, whereas, the ordinary Counter-Ramp type always starts from zero (0) count in each conversion process. In this work, four starting count points is proposed ((00)H, (40)H, (80)H, and (C0)H). For very low level analog input signal, the proposed A/D converter starts from (00)H, and for higher level of input signal the proposed circuit starts from (40)H, and for high input signal level it will start from (80)H or (C0)H depending on signal level value. Increasing these starting counts leads to increase in the conversion speed more and more, but at same time, more analog comparators should be added to the proposed circuit, i.e. the complexity of the circuit will be increased. The proposed circuit is tested practically using 16 and 32 levels of analog input signal, and the results are stimulating. The maximum conversion time value is lower than that of ordinary Counter-Ramp type, where, for the proposed circuit is close to 0.640 µsec, while for ordinary Counter-ramp type its value is close to 2.56 µsec..