DEVELOPMENT of 4-BIT FASTER ALU BASED ON FPGA

Abstract

This paper suggests a developed adder technique called Carry Lookahead Adder (CLA) one of possible solutions based on a 4-bit Fast Arithmetic Logic Unit (ALU), two Mode (Arithmetic/Logic ) functions, and (48) different Operations , to increase the processing speed of an ALU by decreasing gate time delay . The phenomena of ripple carry chain in Ripple Carry Adder (RCA) is an important contributor problem of adder design because every final result depends on the last carry, so the ripple carry adder requires (2n) gate time delay to add two n-bit words. The proposed technique is based on Carry look ahead adder (CLA) to solve this problem. (CLA) structures are considered among the fastest topologies for performing addition because its need only (2(log2 (n)+1)) gate time delay by convert the ripple carry chain into two parameters Propagate (P) and Generate (G) , passed to the cascade connections of single bit (adders), then all the binary results (Fi) exit directly independent on a carry chain , so the adder circuit in an (ALU) will have enhancement speed. The final part of this paper is to simulate the proposed design on Xilinx XC4005E series (FPGA) to get the results, then analyze the results by using two different Mode , in order to get the delay time of all the circuit.